This section provides background information related to the present disclosure which is not necessarily prior art.
A semiconductor light emitting device is manufactured by an EPI process, a chip fabrication process and a package process. However, there can be unexpected events in each manufacturing process, causing the occurrence of defects in a product. If these defects found in the respective manufacturing processes are not eliminated properly in time, it means that a potentially defective product will eventually have to go through post-processing, thereby lowering the overall production yield.
FIG. 1 is a schematic illustration showing an exemplary process of fabricating a semiconductor light emitting chip from a wafer. A disk-shaped wafer is prepared with a raw material such as silicon or sapphire, and this disk-shaped wafer is then subjected to an epitaxial growth process to grow multiple semiconductor layers having a PN junction. Next, the processes of electrode formation, etching and protective film formation are performed to obtain an epi wafer 1 with semiconductor light emitting chips (see FIG. 1a). Then, the epi wafer 1 is attached on a dicing tape 3 as illustrated in FIG. 1b and FIG. 1c, and divided into individual semiconductor light emitting chips 101 by a scribing process as illustrated in FIG. 1d. This is followed by testing, classification, and sorting. For sorting, a sorter 5 as shown in FIG. 1e is used such that semiconductor light emitting chips 101 may be sorted on a fixing layer 13 (e.g., a tape) as shown in FIG. 1f in compliance with regulations required for post-processing such as a packaging process. After that, a visual inspection is carried out.
FIG. 2 is a schematic illustration showing an exemplary process of manufacturing a semiconductor light emitting device package with semiconductor light emitting chips. In a packaging process, semiconductor light emitting chips 101 are die-bonded on a lead frame 4 with a die bonder 501 as shown in FIG. 2a. Then processes including wire-bonding, phosphor encapsulation, property testing, trimming, taping and the like are carried out to produce a semiconductor light emitting device package as shown in FIG. 2b. Optionally, a semiconductor light emitting device package can be produced by mounting semiconductor light emitting chips 101 on a submount with an external electrode formed thereon, such as a PCB. Die bonding indicates a process of bonding semiconductor light emitting chips 101 on a lead frame (for example, 4), PCB or circuit tape, and a die bonder (for example, 501) is a tool used therefor. To keep abreast with an increased trend of smaller semiconductor light emitting chips 101, bonding positions and precise angular positioning of the semiconductor light emitting chips 101 are now more required than ever.
FIG. 3 is a schematic illustration showing an example of semiconductor light emitting chips arrayed on a tape using a sorter. As described with reference to FIG. 1f, semiconductor light emitting chips 101 are sorted and prepared such that they are in compliance with regulations required for post-processing such as a packaging process. The sorter 5 arranges semiconductor light emitting chips 101 on a flat tape 13 in an array of designated rows and columns, maintaining a certain spaced interval from an initially placed semiconductor light emitting chips 101 on the tape 13. In the course of arranging the semiconductor light emitting chips 101, it is possible that any one of them may slightly be turned at an angle (see 15), or the sorter 5 running at high speeds may cause some chips to get thrown off of the tape 13, thereby creating a vacancies 14. A vacancy may also be created by a defective semiconductor light emitting chip 16 that has been taken out based on test results. It could be an option to run the sorter 5 to reduce these problems, but the processing time will be increased by doing so.
If chips in the rows and columns are not arranged in a completely precise manner by the sorter 5, the quality of a product will largely be influenced by the type of a post-process that follows. For example, in the case of bonding the semiconductor light emitting chips 101 on a lead frame 4 with a die bonder 501, the die bonder 501 will recognize a shape of electrodes in a semiconductor light emitting chip 101 bonded onto the tape 13 as well as a shape of the lead frame 4, so as to calibrate position, angle and so on of the chip to be bonded. Therefore, a packaging process is not greatly affected as long as the semiconductor light emitting chips 101 are not arrayed in an abnormally severe condition by the sorter 5. Meanwhile, if the semiconductor light emitting chips 101 arrayed on the tape 13 are to be used directly for a post-process, or rearranged by the sorter 5 to be in compliance with regulations required, any semiconductor light emitting chip 101 that has been skewed or tilted by degrees greater than a given tolerance level will have to be corrected again, and any vacancy will have to be filled with a semiconductor light emitting chip 101. These additional processes lower the process efficiency.
FIG. 4 is a schematic illustration showing an exemplary embodiment of a semiconductor light emitting device depicted in U.S. Pat. No. 6,650,044, in which the semiconductor light emitting device includes a substrate 1200, LEDs and an encapsulant 1000. The LEDs are in the form of flip chips, and include a growth substrate 100 and a stack of layers sequentially deposited on the growth substrate 100, including a first semiconductor layer 300 having a first conductivity type, an active layer 400 for generating light by electron-hole recombination, and a second semiconductor layer 500 having a second conductivity type different from the first conductivity type. A metal reflective film 950 is formed on the second semiconductor layer 500, for reflecting light towards the growth substrate 100, and an electrode 800 is formed on an etched exposed portion of the first semiconductor layer 300. The encapsulant 1000 contains a phosphor, and is formed such that it surrounds the growth substrate 100 and the semiconductor layers 300, 400, 500. A conductive adhesive 830, 970 is used to bond the LEDs to the substrate 1200 having electrical contacts 820, 960.
FIG. 5 is a schematic illustration showing an exemplary embodiment of a method for manufacturing the semiconductor light emitting device depicted in U.S. Pat. No. 6,650,044. Firstly, a plurality of LEDs 2A-2F is placed on the substrate 1200. The substrate 1200 is made of silicon, and a growth substrate 100 (see FIG. 4) of each LED is made of sapphire or silicon carbide. Electrical contact 820, 960 (see FIG. 4) are formed on the substrate 1200, and each LED is bonded to the electrical contacts 820, 960. Next, a stencil 6 having openings 8A-8F corresponding to the LEDs is prepared at the substrate 1200, and an encapsulant 1000 (see FIG. 4) is formed such that the electrical contacts 820, 960 are partially exposed. Later, the stencil 6 is removed, a curing process is carried out, and the substrate 1200 is subjected to sawing or scribing, so as to obtain individual, separated semiconductor light emitting devices.
FIG. 6 is a schematic illustration for describing the problems that can occur while forming an encapsulant collectively for a plurality of semiconductor light emitting chips. Here, after placing guides 21 on the edges of a tape 13 or a substrate, the plurality of semiconductor light emitting chips 101 is covered with an encapsulant 17 which is then pressed flat. However, as described above, there can be vacancies 14 without any semiconductor light emitting chip 101 on the tape 13. In these vacant locations without semiconductor light emitting chips, the encapsulant 17 can sag down slightly, which in turn has an adverse effect on the encapsulant 17 around the neighboring semiconductor light emitting chips 101. As a result, those adversely affected semiconductor light emitting chips (a combination of the encapsulant 17 and the semiconductor light emitting chips 101) may have color coordinates or optical properties different from the intended values.
Because of the aforementioned problems, an additional process may be carried out to rearrange a semiconductor light emitting chip 101 at any vacancy 14 on the tape 13, but this leads to an increase in the number of processes and a decrease in the process efficiency. Meanwhile, instead of taking out a defective semiconductor light emitting chip 16, a process of forming an encapsulant 17 may be performed to prevent the presence of a vacancy from affecting the state of the encapsulant 17. But still, this case also requires an additional process of taking out a defective semiconductor light emitting chip through a visual inspection, and materials are wasted accordingly.
Optionally, after an encapsulant 17 is formed, the encapsulant 17 may be cut with a cutter 31 to obtain individual, separated semiconductor light emitting chips. In this case, however, those cut faces of the encapsulant 17 have a lower light extraction efficiency as they were cut and sectioned with the cutter 31. Moreover, if semiconductor light emitting chips 101 are out of alignment even slightly on the tape 13, a number of defective semiconductor light emitting chips may occur during the cutting process with the cutter 31.